Styx: 16 Bit Instruction Set & CPU Simulation

STYX is a 16-bit RISC CPU simulator designed for educational purposes and compiler research. The project implements a minimal instruction set architecture with 16 instructions, a complete cycle-accurate (Fetch-Decode-Execute) simulator written in C, and an interactive terminal user interface for program visualization. The ISA follows RISC principles with fixed 16-bit instruction encoding, load/store architecture, and composable instruction patterns. The simulator achieves full instruction coverage with comprehensive testing, executing programs including loops, function calls, and memory operations. The Python-based TUI provides real-time visualization of CPU state, enabling step-by-step debugging and educational demonstrations. STYX demonstrates fundamental computer architecture concepts while remaining simple enough to understand fully, making it suitable for teaching assembly programming, ISA design, and as a potential LLVM compiler backend target.